• Quad PLL frequency translation from a common input

• <150 fs typical rms integrated jitter performance

• LVPECL, CML, HCSL, LVDS and LVCMOS Outputs

• Synchronized, holdover or free run operation modes

• Hitless input clock switching: Auto or manual

• Lower Phase noise to minimizing bit error rate in the system

• Better signal integrity helps designer ease implementation and project faster time to market

• Higher function integration reduce system BOM 

• OTN/PTN

• BBU/RRU

• LAN Switch/Router

• Small Cell

• Acceleration card