• Fully Flexible Output and Input Mux: High level of flexibility in output allocation for PLLs

• JESD204B/C Support for data converter clocks

• 1 PPS Input / Output Support with sub 20s lock time

• External EEPROM Support

• TDC Mode available on all input clocks to measure input delays with < 10 ps accuracy: 10 TDC Channels available (independent of the PLLs)

• Lower Phase noise to minimizing bit error rate in the system

• Better signal integrity helps designer ease implementation and project faster time to market

• Higher function integration reduce system BOM 

• OTN/PTN

• BBU/RRU

• LAN Switch/Router

• Small Cell

• SyncE Ethernet