• 输出频率范围:
    0.5 Hz-2.94912 GHz
  • 相位噪声:
    <120fs rms jitter
  • 输入/输出:
    5 inputs / 12 outputs
  • 封装类型:

• Quad PLL frequency translation from any of 4 inputs

• IEEE1588/SyncE/1 PPS support with 1 PPS input lock time <20s

• Best-in-class Digitally Controlled Oscillator (DCO) mode and Hitless switching 

• Time-to-Digital Converter (TDC) Mode available on all input clocks to measure input delays with < 10 ps accuracy: 10 TDC channels available (independent of the PLLs)

• Internal ZDB Mode with <0.5 ns Input-to-Output delay variation

System Benefits

• Lower phase noise minimizes bit error rate and increases design margin in Nx 56G/112G PAM4 I/O systems

• Better signal integrity increases design margin and leads to faster time to market

• Higher clock tree integration reduces system BOM and increases overall reliability




• 100/200/400G/800G Switch/Router with SyncE support

• Small Cell

• Acceleration card