AU5329去抖时钟
  • 输出频率范围:
    up to 2.1GHz
  • 相位噪声:
    <150fs rms jitter
  • 输入/输出:
    2 inputs / 10 outputs
  • 封装类型:
    64-QFN
AU5329
Features

• Dual PLL frequency translation from 1 of 4 inputs

• DPLL Programmable Bandwidth 1mHz- 4KHz

• Digitally Controlled Oscillator (DCO) Mode Frequency Step Resolution: 0.005 ppb

• Hitless input clock switching: Auto or manual, Maximum phase hit of only 50 ps

• ZDM supported with external feedback connection


System Benefits

• Lower phase noise minimizes bit error rate in the system

• Better signal integrity increases design margin and leads to faster time to market

• Higher clock tree integration reduces system BOM and increases overall reliability

Applications

• OTN/PTN

• BBU/RRU

• LAN Switch/Router with SyncE support

• Small Cell

• Acceleration card